Description
Build and run the UVM verification environment for one of our top-level subsystems. You'll write scoreboards + constrained-random stimulus, drive coverage closure, and hand off bug reports to the design team with minimal noise.
Strong candidates have
- 4+ years UVM / SystemVerilog verification
- Experience with formal tools (JasperGold a plus)
- Comfort writing reusable sequences + functional-coverage models
- Willingness to own test-plan authorship, not just test writing
Required skills
uvm
systemverilog
functional coverage
constrained random
verification planning
Nice to have
jaspergold
python
cadence xcelium
synopsys vcs
