Description
Join our design team working on our next inference ASIC (tape-out planned for Q4 2026). You'll own a top-level block (~300k gates) end-to-end: spec → microarchitecture → RTL → synthesis → timing closure with our PD team.
Must-haves
- 6+ years SystemVerilog RTL for ≥10nm silicon
- Experience closing timing on a block-level design
- Solid on clock-domain crossings, reset strategy, low-power (UPF/CPF)
- At least one taped-out chip you can talk about in detail
Ideal extras
- NN accelerator architecture background (MAC arrays, tiling, SRAM banking)
- Worked with on-chip networks (AXI, NoC topologies)
- Some verification / UVM crossover
Required skills
systemverilog
rtl design
microarchitecture
synthesis
timing closure
clock domain crossing
Nice to have
axi
uvm
power analysis
synopsys design compiler
